1. Field of the Invention
This invention is related to the field of processors and, more particularly, to an efficient shifting mechanism in a queue.
2. Description of the Related Art
Today's microprocessors have many varying, sometimes conflicting, requirements. For example, on the one hand, performance is a prime concern and may override other concerns. On the other hand, power consumption may be a prime concern. In other cases, a balance between performance and power consumption is a goal.
In processors, instruction schedulers are frequently used to keep track of program ordering information—in addition to various other control and data fields which may be required for instruction execution. Although it may be possible for many fields to be stored in static or non-shifting arrays, one approach to determining program order is to store some critical fields in a shifting structure that always maintains program dispatch ordering. In such a case it is generally necessary to design an appropriate shifting algorithm to manage the movement of the elements of the shifting arrays. In a case where only a single instruction or operation may be dispatched to a given scheduler in a clock cycle, the design of an efficient shifting algorithm may be relatively straightforward. However, in the more complex case of dispatching multiple instructions or operations to a single scheduler in one clock cycle, there are many different possible shifting algorithms, many of which may be inefficient in terms of shifting and power consumption.
Accordingly, an efficient method and mechanism for shifting data in queues or arrays is desired.